This invention is related to the assignee's co-pending applications:                Ser. No. 12/380,318, which is entitled “ON-CHIP CALIBRATION SYSTEM AND METHOD FOR INFRARED SENSOR” and filed Feb. 26, 2009;        Ser. No. 12/456,910, entitled “METHOD AND STRUCTURES FOR ETCHING CAVITY IN SILICON UNDER DIELECTRIC MEMBRANE” and filed on Jun. 24, 2009;        Ser. No. 12/454,257 (now U.S. Pat. No. 8,026,177), which is entitled “SILICON DIOXIDE CANTILEVER SUPPORT AND METHOD FOR SILICON ETCHED STRUCTURES” and filed on May 14, 2009;        Ser. No. 13/208,130, which is entitled “SILICON DIOXIDE CANTILEVER SUPPORT AND METHOD FOR SILICON ETCHED STRUCTURES” and filed on Aug. 11, 2011; and        Ser. No. 13/208,098, which is entitled “SILICON DIOXIDE CANTILEVER SUPPORT AND METHOD FOR SILICON ETCHED STRUCTURES” and filed on Aug. 11, 2011.        
The present invention relates generally to various semiconductor-processing-compatible infrared (IR) sensor structures and fabrication methods, and more particularly to improved IR radiation sensing structures and processes which reduce size and cost of IR sensors and which provide smaller, more economical, more sensitive IR radiation intensity measurements.
The closest prior art is believed to include the article “Investigation Of Thermopile Using CMOS Compatible Process and Front-Side Si Bulk Etching” by Chen-Hsun-Du and Chengkuo Lee, Proceedings of SPIE Vol. 4176 (2000), pp. 168-178, incorporated herein by reference. Infrared thermopile sensor physics and measurement of IR radiation using thermopiles are described in detail in this reference. Prior Art FIG. 1 herein shows the CMOS-processing-compatible IR sensor integrated circuit chip in FIG. 1 of the foregoing article. “Prior Art” FIG. 1 herein is similar to that drawing.
Referring to Prior Art FIG. 1 herein, the IR sensor chip includes a silicon substrate 2 having a CMOS-processing-compatible dielectric (SiO2) stack 3 thereon including a number of distinct sub-layers. A N-type polysilicon (polycrystalline silicon) trace 11 and an aluminum trace M1 in dielectric stack 3 form a first “thermopile junction” where the polysilicon trace and the aluminum trace are joined. Additional oxide layers and additional metal traces also may be included in dielectric stack 3. An oxide passivation layer 12A is formed on top of dielectric stack 3, and a nitride passivation layer 12B is formed on oxide passivation layer 12A. A number of silicon etchant openings 24 extend through nitride passivation layer 12 and dielectric stack 3 to the top surface of silicon substrate 2 and are used to etch a cavity 4 in silicon substrate 2 underneath the portion of dielectric stack 3 in which the thermopile is formed, to thermally isolate it from silicon substrate 2.
A second thermopile junction (not shown) is also formed in dielectric stack 3 but is not thermally isolated from silicon substrate 2 and therefore is at the same temperature as silicon substrate 2. The temperatures of the first and second thermopile junctions are designated T1 and T2, respectively. The first and second thermopile junctions are connected in series and form a single “thermopile”. The various silicon etchant openings 24 are formed in regions in which there are no polysilicon or aluminum traces, as shown in the dark areas in FIG. 2 of the Du and Lee article.
Incoming IR radiation indicated by arrows 5 in Prior Art FIG. 1 impinges on the “front side” or “active surface” of the IR sensor chip. (The “back side” of the chip is the bottom surface of silicon substrate 2 as it appears in Prior Art FIG. 1.) The incoming IR radiation 5 causes the temperature of the thermopile junction supported on the “floating” portion of dielectric membrane 3 located directly above cavity 4 to be greater than the temperature of the second thermopile junction (not shown) in dielectric membrane 3 which is not insulated by cavity 4.
The IR radiation sensor in Prior Art FIG. 1 measures the temperature difference T1−T2 and produces an output voltage proportional to that temperature difference. The aluminum trace and N-type polycrystalline silicon trace of which the first and second thermopile junctions are formed both are available in a typical standard CMOS wafer fabrication process.
A polycrystalline silicon heater is shown in FIG. 2 of the Du and Lee article, and is described as providing a given bias leading to thermopile power generation used to characterize the thermal conductance and capacitance of the thermopile membrane materials.
The prior art laboratory approach to calibrating thermopile responsivity requires a previously calibrated infrared radiation source. The IR sensor is illuminated by a known IR source, and the resulting value of Vout is measured. Then a somewhat complicated calculation of the infrared power being absorbed by the thermopile is performed in order to determine the responsivity in volts per watt. The prior art calibration procedure is very sensitive to the equipment set-up and to the variances and accuracy of the various components of the equipment set-up.
The Du and Lee article describes the IR sensor mounted inside a metal package having a window through which ambient IR radiation passes to reach the thermopile in the packaged IR sensor chip. The IR sensor chip described in the Du and Lee article is not believed to have ever been commercially available.
The prior art also includes the commercially available MLX90614 family of IR radiation sensors marketed by Melexis Microelectronic Integrated Systems. These devices are packaged in metal TO-39 packages having windows through which impinging IR radiation can pass in order to reach the packaged IR sensors.
The above described prior art IR sensors require large, expensive packages. The foregoing prior art IR radiation sensors need to block visible light while transmitting IR radiation to the thermopiles in order to prevent false IR radiation intensity measurements due to ambient visible lighting conditions. To accomplish this, the packages typically have a silicon window or a window with baffles. Furthermore, the “floating” portion of dielectric membrane over cavity 4 in Prior Art FIG. 1 is quite fragile. In many of the prior art IR sensors, the silicon cavity is etched from the “back side” of the silicon wafer. This creates a large opening span that is difficult to protect.
It would be highly desirable to provide smaller, more economical, and more robust IR sensors than are known in the prior art for various applications such as non-contact measurement of temperature and remote measurement gas concentrations. It is believed that many markets would be very receptive to substantially smaller, substantially more economical IR radiation sensor devices than those of the prior art.
Thus, there is an unmet need for an IR radiation sensor which is substantially smaller and less expensive than the IR radiation sensors of the prior art.
There also is an unmet need for a more accurate IR radiation sensor than has been found in the prior art.
There also is an unmet need for an IR radiation sensor which provides more sensitive, more accurate measurement of IR radiation than the IR radiation sensors of the prior art.
There also is an unmet need for a CMOS-processing-compatible IR radiation sensor chip which does not need to be packaged in a relatively large, expensive package having a window.
There also is an unmet need for a CMOS-processing-compatible IR radiation sensor chip which is substantially more robust than those of the prior art.
There also is an unmet need for an improved method of fabricating an infrared radiation sensor.
There also is an unmet need for an improved method of fabricating a CMOS-processing-compatible IR sensor device which does not require bonding the CMOS-processing-compatible IR sensor chip in a relatively large, expensive package having an infrared window therein.